Publications
2026
-
Towards Efficient and Expressive Offline RL via Flow Anchored Noise-conditioned Q-Learning
Sungyoung Lee, Dohyeong Kim, Eshan Balachandar, Zelal Su Mustafaoglu, Keshav K. Pingali
ICML 2026 Paper Code Blog Post
TL;DR: Offline distributional RL that achieves SOTA robotics task success rates with efficient training and inference.
-
AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
Yao Lai, Souradip Poddar, Sungyoung Lee, Guojin Chen, Mengkang Hu, Bei Yu, Ping Luo, David Z. Pan
TL;DR: First training-free multimodal LLM framework for end-to-end analog design, unifying topology generation and sizing with waveform/log feedback.
-
DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining
Sungyoung Lee, Yao Lai, Ziyi Wang, Seunggeun Kim, Taekyun Lee, David Z. Pan
arXiv 2026 Paper Code Blog Post
TL;DR: First self-supervised pretraining for transistor-level circuits, using simulation-free graph data augmentation.
2025
-
PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning
Seunggeun Kim, Ziyi Wang, Sungyoung Lee, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan
TL;DR: Performs Pareto-aware analog sizing with goal-conditioned reinforcement learning for robust trade-offs across process and operating conditions.
-
AnalogCoder: Analog Circuit Design via Training-Free Code Generation
Yao Lai, Sungyoung Lee, Guojin Chen, Souradip Poddar, Mengkang Hu, David Z. Pan, Ping Luo
TL;DR: Training-free LLM agent for analog circuit design using feedback prompts plus a circuit library; high success rate and 25 designed circuits, outperforming GPT-4o.
2024
-
Analog Transistor Placement Optimization Considering Nonlinear Spatial Variations
Supriyo Maji, Sungyoung Lee, David Z. Pan
DATE 2024 Paper
TL;DR: Simulated annealing transistor placement handles nonlinear spatial variation in analog circuits, beats prior methods, satisfies layout constraints, and improves optimization control.
2022
-
A 10-to-12-GHz Dual Loop Quadrature Clock Corrector in 28-nm CMOS Technology
Jung-Woo Sull, Sungyoung Lee, Deog-Kyoon Jeong
ITC-CSCC 2022 Paper
TL;DR: Dual-loop quadrature clock corrector in Samsung 28-nm CMOS.